Design Flow and Design Environment for System LSIs

OVERVIEW: Progress in process technology has led to extraordinary increases in the number of gates that can be fabricated on a single chip, so it can be said that the age of system LSI has truly begun. To design largescale system LSIs in a short period of time, a revolutionary change in design productivity is required. Important changes for reducing design time include reuse of existing design assets by packaging them as intellectual property (IP), and technology for partitioning hardware and software for co-design and co-verification. Chip design has changed because it is now necessary to efficiently design system LSIs that are larger in scale and operate at high speeds. Technologies including cycle-base simulation, static timing verification, and logic equivalency verification (formal verification) have all been improved to rapidly perform logic and timing verification. Today change is required to achieve a total design and verification environment for lower power consumption together with test design for system LSIs with a multitude of diverse components on chip. We expect to incorporate these new design technologies in a design kit that we will provide for existing design environments to assemble a total design environment. Tsuyoshi Takahashi Kei Suzuki Kazuyuki Nomoto